1. Field of the Invention
The present invention relates to a semiconductor integrated circuit comprising a phase-locked-loop circuit, and particularly, to a master-slice type semiconductor integrated circuit such as a gate array.
2. Description of the Prior Art
In general, in a single device which is comprised of a plurality of semiconductor integrated circuits (hereinafter "LSI"), it is necessary to assure synchronization of phase between the plurality of LSIs by use of a common clock signal. In this case, the phase of the common clock signal arrived at an internal circuit of one LSI is different from the phase of the common signal arrived at an internal circuit of other LSI. In addition, even within the internal circuit of the same LSI, depending on the arrangement of elements within the LSI, the phases of clock signals supplied to the respective elements become different from each other. Of these phase differences, which presents a problem in terms of circuit operation, the former is known as an inter-chip skew and the latter is known as an inner-chip skew.
According to a method proposed as a solution of the inter-chip skew, a phase-locked-loop circuit (hereinafter "PLL circuit") is provided in each LSI and the phase of a clock within the LSI is monitored and synchronized to the phase of a common clock signal. Such a technique is disclosed in, for example, Japanese Patent Laid-Open Gazette No. 2-224104.
FIG. 9 is a plan view showing a circuit structure of a plurality of LSIs which are arranged on a circuit board. FIG. 9 explains the proposed method above. LSIs 70A, 70B and 70C comprise internal circuits 71A, 71B and 71C, PLL circuits 72A, 72B and 72C, and driver circuits 76A, 76B and 76C, respectively.
An external clock signal 73 is supplied commonly to the LSIs 70A, 70B and 70C. The internal circuits 71A, 71B and 71C are connected with each other by a bus line 74.
In the LSI 70A, a clock signal is supplied from the driver circuit 76A to the internal circuit 71A wherein it is distributed to elements which are formed within the internal circuit 71A. One of the distributed clock signals is monitored as an internal clock signal 75A. That is, the internal clock signal 75A is inputted to the PLL circuit 72A and its phase is compared with the phase of the external clock signal 73. The PLL circuit 72A and the driver circuit 76A operate so as to synchronize the phase of the internal clock signal 75A to the phase of the external clock signal 73.
This is also performed within the other LSIs 70B and 70C respectively on internal clock signals 75B and 75C by the PLL circuits 72B and 72C and the driver circuits 76B and 76C. Hence, the phases of the internal clock signals 75A, 75B and 75C which are respectively used in the LSIs 70A, 70B and 70C are commonly synchronized to the phase of the external clock signal 73, with a result that the inter-chip skew is improved.
Having such a construction as above, conventional LSIs can improve the inter-chip skew. However, the inner-chip skew still remains as a problem within each one of the internal circuits 71A, 71B and 71C. The internal circuit 71A is taken as an example wherein the internal clock signal 75A taken from a certain element of the internal circuit 71A is synchronized in terms of phase to the external clock 73. In the internal circuit 71A, the closer the element is to the driver circuit 76A, the greater phase lead the clock signal has with respect to the external clock. Conversely, the farther the element is from the element from which the internal clock signal 75A was taken, the greater phase lag the clock signal has with respect to the external clock.
Hence, if the element from which the internal clock signal 75A is taken is selected optionally, in the worst event, the inter-chip skews between the LSIs will increase by the amount of the inner-chip skew. For this reason, in selecting an element wherefrom the internal clock signal 75A is taken, it is necessary to standardize between the LSIs what phase of the inner-chip skew the clock to be selected is to have.
However, since the internal circuit 71A is automatically arranged and wired to form a gate array, or a semicustom device, depending on the arrangement of the elements, not only the inner-chip skew will increase but also the location of an element from which the internal clock signal 75A is taken changes. Hence, the range of distribution of the inner-chip skew with respect to the external clock signal 73 cannot be set as desired, making it impossible to sufficiently control the inter-chip skew.
A solution of this problem is to insert a delay circuit between the internal circuit 71A and the PLL circuit 72A after the internal circuit 71A is arranged and wired, to delay of the internal clock 75A and to adjust the phase difference. In this case, however, the phases cannot be adjustment properly if a delay created by the delay circuit is changed due to, for instance, heating up of the LSI.